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An efficient H.264 intra frame coder system design

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Hamzaoğlu, İlker and Taşdizen, Özgür and Şahin, Esra (2007) An efficient H.264 intra frame coder system design. In: 15th IFIP International Conference on VLSI-SoC, Atlanta, Georgia, USA

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Official URL: http://dx.doi.org/10.1109/VLSISOC.2007.4402498

Abstract

In this paper, we present an efficient H.264 / MPEG4 Part 10 Intra Frame Coder System. The system achieves real-time performance for portable applications with low hardware cost, and it includes a novel intra prediction hardware design. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code works at 71 MHz in a Xilinx Virtex II FPGA and it code 35 CIF frames (352×288) per second. The system also includes a software running on an Arm926EJS processor for implementing pre-processing and post-processing functions. The H.264 Intra Frame Coder hardware and software are demonstrated to work together on an Arm Versatile Platform development board.

Item Type:Papers in Conference Proceedings
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
ID Code:10731
Deposited By:İlker Hamzaoğlu
Deposited On:15 Nov 2008 14:47
Last Modified:22 Jul 2019 11:16

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