A front-end integrated circuit for 3D acoustic imaging using 2D capacitive micromachined ultrasonic transducer arrays
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Çiçek, İhsan (2004) A front-end integrated circuit for 3D acoustic imaging using 2D capacitive micromachined ultrasonic transducer arrays. [Thesis]
Official URL: http://risc01.sabanciuniv.edu/record=b1124914 (Table of Contents)
Integration of front-end circuits with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present a front-end drive-readout integrated circuit suitable for 2D CMUT arrays used in 3D ultrasonic imaging. The circuit consists of a pulser for driving the CMUT array element by a high voltage pulse, a metal pad for connection to the CMUT element, a low noise readout amplifier for buffering the received echo signal, and a switch for protecting the inputs of the readout amplifier not only from the DC bias of the CMUT but also from the high voltage pulses in transmit mode. We developed an equivalent electrical model for simulating the CMUT, where the model parameters were obtained through a finite element analysis using ANSYS. Based on this model we performed the prc-layout simulations for each sub-circuit using the Cadence Spectre Simulator, where a 10pF load capacitance was assumed to model the routing and off-chip parasitic capacitances. The layout of the circuit fits into 200 x 2QQfj,m2 area that satisfies the Nyquist spatial sampling requirement for a 2D transducer aperture operating at 3-5 MHz. We also performed post-layout simulations using the extracted circuit by Cadence Spectre and compared the results with the pre-Iayout simulation results to examine the possible effects of the parasitic components on circuit performance. We observed that the prc- and post-layout simulations were in agreement, proving the validity of our electrical model. The equivalent input noise at the input of the readout amplifier was measured as 6.45 nV/y/Wz. An experimental chip consisting of 4x4 array of circuit cells was formed for the initial test studies and scheduled for fabrication in AMS 0.8 \x m, 50V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding or CMUT-on-CMOS process.
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