Dynamic power reduction in digital pixel design for large format focal plane arrays

Shafique, Atia and Kayahan, Hüseyin and Afridi, Sohaib Saadat and Ceylan, Ömer and Yazıcı, Melik and Abbasi, Shahbaz and Galioğlu, Arman and Gürbüz, Yaşar (2016) Dynamic power reduction in digital pixel design for large format focal plane arrays. Microelectronics Journal, 58 . pp. 9-13. ISSN 0026-2692 (Print) 1879-2391 (Online)

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Official URL: http://dx.doi.org/10.1016/j.mejo.2016.10.003


This paper presents a design and analytical approach to significantly reduce the dynamic power consumption of front-end pixel design for digital readout integrated circuits (DROICs) in digital pixel sensor (DPS) arrays. DPS architecture relies on coarse quantization with pulse frequency modulation (PFM) and a novel approach of extended integration incorporated to achieve lower noise. The design is fabricated in 90 nm CMOS process with pixel pitch of 30 µm. Proposed architecture can attain eminently high charge handling capacity of 2.2Ge- with a quantization noise of 1072e- and extremely low power dissipation of 14.28 mW. The proposed dynamic power reduction paradigm enables to alleviate the overall power consumption to 35% as compared to state-of- art PFM based 256×256 DPS array with the lowest Figure of Merit (FoM) of 297fJ/LSB reported earlier. The power reduction escalates further for higher detector currents and large format Focal Plane Arrays (FPA). The proposed design is tested and compared to our previous DROIC measurement results and other works in terms of power and quantization noise.

Item Type:Article
Uncontrolled Keywords:Digital readout integrated circuits (DROIC); Focal Plane array (FPA); Pixel parallel ADC; Pulse frequency modulation (PFM); Extended integration; Quantization noise; High dynamic range (HDR)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
ID Code:31270
Deposited By:Melik Yazıcı
Deposited On:04 May 2017 12:20
Last Modified:04 May 2017 12:20

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