title   
  

A high performance deblocking filter hardware for high efficiency video coding

Özcan, Erdem and Adıbelli, Yusuf and Hamzaoğlu, İlker (2013) A high performance deblocking filter hardware for high efficiency video coding. IEEE Transactions on Consumer Electronics, 59 (3). pp. 714-720. ISSN 0098-3063

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Official URL: http://dx.doi.org/10.1109/TCE.2013.6626260

Abstract

The recently developed High Efficiency Video Coding (HEVC) international video compression standard uses adaptive deblocking filter for reducing blocking artifacts. Deblocking filters increase both subjective and objective quality. But, they have high computational complexity. Therefore, in this paper, the first HEVC deblocking filter hardware in the literature is proposed. Two parallel datapaths are used in the proposed hardware in order to increase its performance. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code is verified to work correctly on an FPGA board. The proposed HEVC deblocking filter hardware can code 30 full HD (1920x1080) video frames per second. Therefore, it can be used in consumer electronics products that require a real-time HEVC encoder or decoder.(1)

Item Type:Article
Uncontrolled Keywords:HEVC; Deblocking Filter; Hardware Implementation; FPGA
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK5101-6720 Telecommunication
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK1-4661 Electrical engineering. Electronics Nuclear engineering
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
ID Code:23292
Deposited By:İlker Hamzaoğlu
Deposited On:14 Jan 2014 11:47
Last Modified:14 Jan 2014 11:47

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