title   
  

A reconfigurable frame interpolation hardware architecture for high definition video

Taşdizen, Özgür and Hamzaoğlu, İlker (2009) A reconfigurable frame interpolation hardware architecture for high definition video. In: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, Patras, Greece

[img]
Preview
PDF (This is a RoMEO green publisher (Can archive pre-print and post-print or publisher's version/PDF)) - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader
256Kb

Official URL: http://dx.doi.org/10.1109/DSD.2009.216

Abstract

Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorithms has become very important. Therefore, in this paper, we propose a low cost hardware architecture for realtime implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it allows adaptive selection of frame interpolation algorithms for each Macroblock. The proposed hardware architecture is implemented in VHDL and mapped to a low cost Xilinx XC3SD1800A-4 FPGA device. The implementation results show that the proposed hardware can run at 101 MHz on this FPGA and consumes 32 BRAMs and 15384 slices.

Item Type:Papers in Conference Proceedings
Uncontrolled Keywords:Frame Rate Up-Conversion, Frame Interpolation, Hardware Implementation, FPGA.
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
ID Code:12418
Deposited By:İlker Hamzaoğlu
Deposited On:01 Nov 2009 22:08
Last Modified:25 May 2011 14:18

Repository Staff Only: item control page