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A High performance and low cost hardware arcitecture for H.264 transform and quantization algorithms

Taşdizen, Özgür and Hamzaoğlu, İlker (2005) A High performance and low cost hardware arcitecture for H.264 transform and quantization algorithms. In: 13th European Signal Processing Conference, Antalya

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Abstract

In this paper, we present a high performance and low cost hardware architecture for real-time implementation of forward transform and quantization and inverse transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard. The hard-ware architecture is based on a reconfigurable datapath with only one multiplier. This hardware is designed to be used as part of a complete low power H.264 video coding system for portable appli-cations. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 81 MHz in a Xilinx Virtex II FPGA and it is verified to work at 210 MHz in a 0.18´ ASIC implementation. The FPGA and ASIC implementations can code 27 and 70 VGA frames (640x480) per second respectively.

Item Type:Papers in Conference Proceedings
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
ID Code:1238
Deposited By:Özgür Taşdizen
Deposited On:17 Dec 2006 02:00
Last Modified:29 Aug 2007 14:16

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