Effect of DAC non-idealities in computational accuracy of in memory dot product accelerator

Official URL: https://dx.doi.org/10.1109/ELECO69582.2025.11329377

Traditional computing platforms are based on the von Neumann architecture, which consists of separate units for computing and storage. Data-intensive tasks require frequent data transfers between these units, reducing energy efficiency and overall throughput. This triggered the development of computing paradigms beyond von Neumann, such as Processing in Memory (PiM) architectures. Various works have demonstrated that a standard 8-transistor (8T) SRAM array can be used in analog-like dot product operations. However, these computations require highly linear peripheral circuitry, such as digital-to-analog converters (DAC). In this work, we analyze the effect of analog non-idealities of the DAC circuit on the computational accuracy of an 8T SRAM array. We propose using a resistor string DAC architecture to generate the analog encoded input vector. An analysis was performed on 65 nm CMOS. Inference accuracy was evaluated on the MNIST dataset using a MLP network, which changed the accuracy from 96.36% to 96.18%.