A partially pixel-parallel DROIC for MWIR imagers with columnwise residue quantization

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Official URL: http://dx.doi.org/10.1109/TED.2018.2871172

This paper presents a partially pixel-parallel digital readout integrated circuit that overcomes the limitation of achievable digital resolution seen in megapixel-format infrared digital focal plane arrays (IR-DFPAs). It incorporates 5-bit in-pixel pulse frequency modulation (PFM)-based charge-to-digital converters and 10-bit successive approximation register (SAR) column analogto-digital converters (ADCs). To increase the readout resolution, the residue charge at the end of the integration phase is fine converted to a 10-bit digital word and combined with the in-pixel data. This method is a compromise between fully pixel-parallel and fully column-parallel conversion approaches and favors the ever-growing trend toward small pitch FPAs by allowing a compact pixel size. A prototype consisting of a 32 x 32 array of pixels, 32 column SAR ADCs, and a timing controller block is designed and fabricated in a 90-nm bulk CMOS process. A modified version of the conventional PFM-based pixel is designed to help hold the residue charge. The design is targeted at medium-wave IR-DFPAs with frame rates up to 400 Hz. A signal-to-noise ratio of 79 dB is achieved with a full-well capacity of 2.4 Me-.