A 6-Bit time-interleaved asynchronous successive approximation register analog-to digital converter with 1-bit redundancy in 90nm technology
Galioğlu, Arman (2017) A 6-Bit time-interleaved asynchronous successive approximation register analog-to digital converter with 1-bit redundancy in 90nm technology. [Thesis]
High speed ADC architectures constitute the heart of many di erent applications such as wireless and wireline communication systems, instrumentation systems, data acquisition systems. A 6-bit, 700MSps low power successive approximation register (SAR) analog-to-digital converter (ADC) with 1-bit redundancy has been designed and fabricated in 90nm CMOS process. The speed of 700 MSps is achieved by time-interleaving four fully di erential asynchronous SAR sub-ADC channels each of which achieves approximately 178 MSps data rate. A full custom digital path that speeds up the asynchronous SAR loop control path has been implemented to achieve this single channel data rate along with 1-bit redundancy to reduce the errors from settling time of the capacitive digital-to-analog converter (CDAC). The capacitive DAC (CDAC) is based on a full di erential VCM-based switching scheme which reduces the overall switching energy. The time-interleaved structure includes a lowskew non-overlapping clock generation circuit to reduce possible timing skew mismatch between the interleaved channels. The ADC works with 1.2V power supplies, 1V and 0.5 V references and a 700MHz clock. Three di erent ADC prototypes have been implemented the single channel, two channel and four channel time-interleaved ADCs are given in this thesis. The SNDR, ENOB of the single channel ADC are 37.4dB, 5.94 bits for fin << fs and degrades to 29.4 dB at fin = fs=2. The time interleaved circuit achieves a 0.28 LSB INL/0.24 DNL in simulation without any calibration. The Walden Figure of Merit is calculated to be 181.8 fJ/conv-step and the Schreier Figure of Merit is found to be 143.53 dB.
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