title   
  

A computation and energy reduction technique for HEVC intra prediction

Azgın, Hasan and Kalalı, Ercan and Hamzaoğlu, İlker (2017) A computation and energy reduction technique for HEVC intra prediction. IEEE Transactions on Consumer Electronics, 63 (1). pp. 36-43. ISSN 0098-3063 (Print) 1558-4127 (Online)

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Official URL: http://dx.doi.org/10.1109/TCE.2017.014728

Abstract

Intra prediction algorithm used in High Efficiency Video Coding (HEVC) standard has very high computational complexity. Therefore, in this paper, a novel technique is proposed for reducing amount of computations performed by HEVC intra prediction algorithm and, therefore, reducing energy consumption of HEVC intra prediction hardware. The proposed technique significantly reduced the amount of computations performed by 4x4, 8x8, 16x16 and 32x32 luminance angular prediction modes. The proposed technique does not affect the PSNR and bit rate. In this paper, a low energy HEVC intra prediction hardware for 4x4, 8x8, 16x16 and 32x32 angular prediction modes is also designed and implemented using Verilog HDL. The proposed technique significantly reduced the energy consumption of the HEVC intra prediction hardware. Therefore, it can be used in portable consumer electronics products that require a real-time HEVC encoder.

Item Type:Article
Uncontrolled Keywords:HEVC; Intra Prediction; Hardware Implementation; FPGA; Energy Reduction
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
ID Code:33732
Deposited By:İlker Hamzaoğlu
Deposited On:10 Sep 2017 18:34
Last Modified:10 Sep 2017 18:34

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