title   
  

Pulse frequency modulated DROICs with reduced quantization noise employing extended counting method

Kayahan, Hüseyin (2013) Pulse frequency modulated DROICs with reduced quantization noise employing extended counting method. [Thesis]

[img]PDF - Registered users only - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader
5Mb

Official URL: http://risc01.sabanciuniv.edu/record=b1534422 (Table of Contents)

Abstract

Reducing the system size and weight is a very competitive advantage in today’s IR market. A continuously growing effort has been shown to achieve digital output ROICs over the last decade with a primary concern to reduce the overall imaging system size and power by eliminating off chip ADCs and precise analog buffers as well as reducing the size of periphery boards. There is an unnamed industry standard of 20mK NETD for military IR imaging applications. A lower value is always desired to improve image quality or for track and search systems higher correct decision probabilities. Photon noise is the primary noise source and follow shot noise behavior and ideal SNR is limited with the square root of the stored charges. The limiting issue for higher SNR is due the limited charge handling capacity in a small pixel area. Recent works have shown DROICs with very high charge handling capacities on the order of giga electrons and SNR values as high as 90dB. The drawbacks of these works are the high quantization noise which makes their use limited to high flux scenes or low frame rate applications and high power dissipation which limits the use to small or moderate size array dimensions. In order to overcome these issues, this thesis has proposed circuit architectures with quantization noise levels lower than 200 electrons with 22 bit representation for a charge handling capacity of 2.34Ge-. The architecture relies on PFM pixel followed by a novel per pixel residue measurement method. A 32x32 prototype array has been fabricated and tested for verification of the proposed architecture. Design considerations have been followed for 256x256 array with a high frame rate of 400Hz and power dissipation of 22.21mW and a peak SNR of 71dB. Additionally low power operation of the proposed DROIC architecture with respect to ordinary PFM DROICs has been analyzed.

Item Type:Thesis
Uncontrolled Keywords:DROIC. -- Quantization Noise. -- HDR. -- PFM. --Extended Counting.
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
ID Code:31131
Deposited By:IC-Cataloging
Deposited On:27 Mar 2017 11:12
Last Modified:27 Mar 2017 11:12

Repository Staff Only: item control page