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Phase error reduction of a digitally controlled phase shifter utilizing a variable phase and gain amplifier

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Özeren, Emre and Çalışkan, Can and Kalyoncu, İlker and Kayahan, Hüseyin and Gürbüz, Yaşar (2016) Phase error reduction of a digitally controlled phase shifter utilizing a variable phase and gain amplifier. Microelectronics Journal, 54 . pp. 9-13. ISSN 0026-2692 (Print) 1879-2391 (Online)

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Official URL: http://dx.doi.org/10.1016/j.mejo.2016.05.006

Abstract

This paper presents a variable phase and gain amplifier (VPGA), featured in a 4-bit digitally controlled phase shifter, that enables significant phase error reduction. The functionality of the VPGA is demonstrated by utilizing it between the third and fourth bits of a digitally controlled phase shifter. The first three bits are implemented using distributed active switches based on HBTs and the fourth bit is realized in a final amplification stage based on switching between common-base (CB) and common-emitter (CE) topologies. By the use of the VPGA, RMS phase error is reduced from 22 degrees to 11 degrees with the cost of reduced gain (0.1-2.5 dB) and increased RMS gain error (1.0-2.2 dB). A total of 360 degrees phase shift is achieved in 4 bit resolution with an RMS phase error of 0.1 degrees at 10.5 GHz, and a maximum 11 phase error in 4.5 GHz bandwidth. The chip area is 2.150 mm x 1.040 mm including pads, and the VPGA consumes only 0.32 mm x 0.410 mm area. The chip is implemented in a 0.25-mu m SiGe BiCMOS process. These performance parameters are attributed to the adjustment method by the VPGA applied in this work, which enables superior performance than the-state-of-the-art utilizing similar technologies.

Item Type:Article
Uncontrolled Keywords:Phase shifters; BiCMOS; Phased arrays; X-band; SiGe BiCMOS; T/R module
Subjects:UNSPECIFIED
ID Code:29845
Deposited By:Yaşar Gürbüz
Deposited On:10 Nov 2016 09:56
Last Modified:10 Nov 2016 09:56

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