title   
  

A computation and energy reduction technique for HEVC discrete cosine transform

Kalalı, Ercan and Mert, Ahmet Can and Hamzaoğlu, İlker (2016) A computation and energy reduction technique for HEVC discrete cosine transform. IEEE Transactions on Consumer Electronics, 62 (2). pp. 166-174. ISSN 0098-3063 (Print) 1558-4127 (Online)

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Official URL: http://dx.doi.org/10.1109/TCE.2016.7514716

Abstract

In this paper, a novel computation and energy reduction technique for High Efficiency Video Coding (HEVC) Discrete Cosine Transform (DCT) for all Transform Unit (TU) sizes is proposed. The proposed technique reduces the computational complexity of HEVC DCT significantly at the expense of slight decrease in PSNR and slight increase in bit rate by only calculating several pre-determined low frequency coefficients of TUs and assuming that the remaining coefficients are zero. It reduced the execution time of HEVC HM software encoder up to 12.74%, and it reduced the execution time of DCT operations in HEVC HM software encoder up to 37.27%. In this paper, a low energy HEVC 2D DCT hardware for all TU sizes is also designed and implemented using Verilog HDL. The proposed hardware, in the worst case, can process 53 Ultra HD (7680x4320) video frames per second. The proposed technique reduced the energy consumption of this hardware up to 18.9%. Therefore, it can be used in portable consumer electronics products that require a real-Time HEVC encoder.

Item Type:Article
Uncontrolled Keywords:HEVC; Discrete Cosine Transform; Hardware Implementation; FPGA; Energy Reduction
Subjects:UNSPECIFIED
ID Code:29583
Deposited By:İlker Hamzaoğlu
Deposited On:02 Sep 2016 14:36
Last Modified:08 Sep 2016 11:55

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