Low-voltage ferroelectric-paraelectric superlattices as gate materials for field-effect transistors

Official URL: http://dx.doi.org/10.1007/s10853-015-9301-9

The demand for new materials to be used in field-effect transistors and similar devices with low energy loss is more than ever before as integrated circuits have become a considerable source of energy consumption. One of the challenges in designing such energy efficient logic devices is finding suitable dielectric materials systems for the gate that controls the drain current in a p-type channel. A fundamental limit for energy efficiency exists in such devices imposed by the polarizability of conventional linear gate dielectrics. Generating on/off states in the channel that differ by at least a million times in the magnitude of the drain current near saturation requires several volts of gate bias for the case of a linear dielectric material in a submicron device. In this study, we demonstrate that ferroelectric-paraelectric superlattice heterostructures can generate the same effect in a p-type channel for bias voltages much lower than in a linear high dielectric constant gate. We consider a metal/superlattice/p-type semiconductor stack for this purpose. Using a thermodynamic model, we show that the multi-domain state of the ferroelectric layers can be tailored and distinct on/off states of the channel are possible for gate bias voltages below 1 V. The origins of such functionality of ferroelectric-paraelectric superlattices are discussed with respect to material characteristics such as the phase transition temperature of the ferroelectric, total polarization, and the dielectric response.