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A high performance and low energy intra prediction hardware for high efficiency video coding

Kalalı, Ercan and Adıbelli, Yusuf and Hamzaoğlu, İlker (2012) A high performance and low energy intra prediction hardware for high efficiency video coding. In: 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), Oslo, Norway

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Official URL: http://dx.doi.org/10.1109/FPL.2012.6339161

Abstract

Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. Therefore, in this paper, we propose novel techniques for reducing amount of computations performed by HEVC intra prediction algorithm, and therefore reducing energy consumption of HEVC intra prediction hardware. The proposed techniques significantly reduce the amount of computations performed by 4×4 and 8×8 angular prediction modes with a small comparison overhead without any PSNR and bit rate loss. We also designed and implemented a high performance HEVC intra prediction hardware for 4×4 and 8×8 angular prediction modes including the proposed techniques using Verilog HDL, and mapped it to a Xilinx Virtex 6 FPGA. The proposed techniques significantly reduce the energy consumption of the proposed hardware on this FPGA.

Item Type:Papers in Conference Proceedings
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
ID Code:20479
Deposited By:İlker Hamzaoğlu
Deposited On:06 Dec 2012 14:53
Last Modified:01 Mar 2014 22:04

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