A computation and energy reduction technique for H.264 deblocking filter hardware (H.264 blok giderici filtre donanımının işlem miktarını ve enerji kullanımını azaltan teknik)
Adıbelli, Yusuf and Parlak, Mustafa and Hamzaoğlu, İlker (2011) A computation and energy reduction technique for H.264 deblocking filter hardware (H.264 blok giderici filtre donanımının işlem miktarını ve enerji kullanımını azaltan teknik). In: IEEE 19th Conference on Signal Processing and Communications Applications (SIU 2011), Antalya, Turkey
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Official URL: http://dx.doi.org/10.1109/SIU.2011.5929624
In this paper, we propose pixel equality based technique to reduce the amount of computations performed by H.264 Deblocking Filter (DBF) algorithm and therefore reduce the energy consumption of H.264 DBF hardware. This technique exploits pixel equality in a video frame by performing a small number of comparisons among edge pixels used in DBF equations before the filtering. If the input pixels are equal, DBF equations simplify significantly. The proposed technique reduces the amount of addition and shift operations performed by H.264 DBF algorithm up to 43% and 55% respectively with a small comparison overhead. The pixel equality based technique does not affect PSNR. We also implemented an efficient H.264 DBF hardware including the proposed technique using Verilog HDL. The proposed pixel equality based technique reduced the energy consumption of this hardware up to 35%.
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