A novel power reduction technique for block matching motion estimation hardware
Akın, Abdulkadir and Ulusel, Onur Can and Özcan, Tevfik Zafer and Sayılar, Gökhan and Hamzaoğlu, İlker (2011) A novel power reduction technique for block matching motion estimation hardware. In: 21st International Conference on Field Programmable Logic and Applications (FPL 2011), Crete, Greece
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Official URL: http://dx.doi.org/10.1109/FPL.2011.54
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. Therefore, in this paper, we propose comparison prediction (CP) technique for reducing the power consumption of block matching (BM) ME hardware. CP technique reduces the power consumption of absolute difference operations performed by BM ME hardware. CP technique can easily be used in all BM ME hardware. In this paper, we applied it to a 256 processing element fixed block size ME hardware implementing full search algorithm. It reduced the average dynamic power consumption of this ME hardware by 2.2% with no Peak Signal-to-Noise Ratio (PSNR) loss and by 9.3% with 0.04% PSNR loss on a XC2VP30-7 FPGA.
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