An adaptive bilateral motion estimation algorithm and its hardware architecture

Abstract

In this paper, we propose an adaptive bilateral motion estimation (Bi-ME) algorithm for frame rate up-conversion of High Definition (HD) video. The proposed algorithm can be used as a refinement step after a true motion estimation algorithm. It refines the motion vector field between successive frames by employing a spiral search pattern and by adaptively assigning weights to candidate search locations. In addition, we propose a high performance hardware architecture for implementing the proposed Bi-ME algorithm. The proposed hardware uses an efficient memory organization and a novel data reuse scheme in order to reduce the memory bandwidth and control overhead. The proposed hardware consumes 24% of the slices in a Xilinx 2V8000FF1517-5 FPGA. It can work at 107 MHz in the same FPGA and is capable of processing 124 1920x1080 full HD frames per second (fps), therefore doubling the frame rate to 248 fps.