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Computation reduction techniques for vector median filtering and their hardware implementation

Taşdizen, Özgür and Hamzaoğlu, İlker (2010) Computation reduction techniques for vector median filtering and their hardware implementation. In: 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2010), Lille, France

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Official URL: http://dx.doi.org/10.1109/DSD.2010.102

Abstract

Vector Median Filters (VMFs) are used in many image and video processing applications. Recently, they are used for Frame Rate Up-Conversion (FRC). However, they are difficult to implement in real-time because of their high computational complexity. Therefore, in this paper, we propose several techniques to reduce the computational complexity of VMFs by using data reuse methodology and by exploiting the spatial correlations in the motion vector field. In addition, we designed and implemented an efficient VMF hardware including the computation reduction techniques exploiting the spatial correlations in the motion vector field on a low cost Xilinx XC3S400A-5 FPGA. The FPGA implementation can work at 145 MHz and it can process more than 94 high definition frames per second.

Item Type:Papers in Conference Proceedings
Uncontrolled Keywords:Computation reduction , frame rate conversion , hardware implementation , vector median filter
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
ID Code:15571
Deposited By:İlker Hamzaoğlu
Deposited On:01 Dec 2010 12:22
Last Modified:01 Dec 2010 12:22

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