title   
  

Low power techniques for motion estimation hardware

Kalaycıoğlu, Çağlar and Ulusel, Onur Can and Hamzaoğlu, İlker (2009) Low power techniques for motion estimation hardware. In: 19th International Conference on Field Programmable Logic and Applications, Prague, Czech Republic

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Official URL: http://dx.doi.org/10.1109/FPL.2009.5272508

Abstract

Motion estimation (ME) is the most computationally intensive and the most power consuming part of video compression and video enhancement systems. In this paper, we propose a novel power reduction technique for ME hardware. We quantified the impact of glitch reduction, clock gating and the proposed technique on the power consumption of two full search ME hardware implementations on a Xilinx Virtex II FPGA using Xilinx XPower tool. Glitch reduction and clock gating together achieved an average of 21% dynamic power reduction. The proposed technique achieved an average of 23% dynamic power reduction with an average of 0.4 db PSNR loss. The proposed technique achieves better power reduction than pixel truncation technique with a similar PSNR loss.

Item Type:Papers in Conference Proceedings
Uncontrolled Keywords:clocks data compression field programmable gate arrays image enhancement low-power electronics motion estimation video coding
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics
ID Code:12416
Deposited By:İlker Hamzaoğlu
Deposited On:01 Nov 2009 21:40
Last Modified:31 May 2010 11:18

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