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An Efficient hardware implementation of the tate pairing in characteristic three

Kömürcü, Giray and Savaş, Erkay (2008) An Efficient hardware implementation of the tate pairing in characteristic three. In: The Third International Conference on Systems, ICONS 2008, Cancun, Mexico

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Official URL: http://dx.doi.org/10.1109/ICONS.2008.27

Abstract

DL systems with bilinear structure recently became an important base for cryptographic protocols such as identity-based encryption (IBE). Since the main computational task is the evaluation of the bilinear pairings over elliptic curves, known to be prohibitively expensive, efficient implementations are required to render them applicable in real life scenarios. We present an efficient accelerator for computing the Tate Pairing in characteristic 3, using the Modified Duursma-Lee algorithm. Our accelerator shows that it is possible to improve the area-time product by 12 times on FPGA, compared to estimated values from one of the best known hardware architecture [6] implemented on the same type of FPGA. Also the computation time is improved upto 16 times compared to software applications reported in [17]. In addition, we present the result of an ASIC implementation of the algorithm, which is the first hitherto.

Item Type:Papers in Conference Proceedings
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7800-8360 Electronics > TK7885-7895 Computer engineering. Computer hardware
ID Code:10225
Deposited By:Erkay Savaş
Deposited On:08 Nov 2008 16:01
Last Modified:08 Nov 2008 16:01

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